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CS3301A
DIGITAL CHARACTERISTICS
CS3301A
Parameter
Symbol
Min
Typ
Max
Unit
Digital Characteristics
High Level Input Drive Voltage
Low Level Input Drive Voltage
Input Leakage Current
Digital Input Capacitance
Rise Times, Digital Inputs Except CLK
Fall Times, Digital Inputs Except CLK
( Note 15 )
( Note 15 )
V IH
V IL
I IN
C IN
t RISE
t FALL
0.6*VD
0.0
-
-
-
-
-
-
±1
9
-
-
VD
0.8
±10
-
100
100
V
V
μ A
pF
ns
ns
Master Clock Specifications
Master Clock Frequency
( Note 16 )
f CLK
2.0
2.048
2.2
MHz
Master Clock Duty Cycle
Master Clock Rise Time
Master Clock Fall Time
Master Clock Jitter (In-Band or Aliased In-Band)
Master Clock Jitter (Out-of-Band)
f DTY
t RISE
t FALL
JTR IB
JTR OB
40
-
-
-
-
-
-
-
-
-
60
25
25
300
1
%
ns
ns
ps
ns
Notes: 15. Device is intended to be driven with CMOS logic levels.
16. When CLK is tied to GND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
t rise
t fa ll
0 .9 * V D
0 .1 * V D
Figure 2. Digital Input Rise and Fall Times
Input Selection
800 ? termination
INA only
INB only
INA + INB
MUX1
0
1
0
1
MUX0
0
0
1
1
Gain Selection
x1
x2
x4
x8
GAIN2
0
0
0
0
GAIN1
0
0
1
1
GAIN0
0
1
0
1
x16
x32
x64
reserved
1
1
1
1
0
0
1
1
0
1
0
1
Table 1. Digital Selections for Gain and Input Mux Control
DS757F1
7
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